1. Technical Field
The present invention relates to an apparatus for data processing in general, and in particular to an apparatus for altering bits within an instruction. Still more particularly, the present invention relates to an apparatus for adjusting a STORE instruction having memory hierarchy control bits.
2. Description of the Prior Art
Typically, Reduced Instruction Set Computing (RISC) processors have fewer instructions than their Complex Instruction Set Computing (CISC) counterparts. Thus, to a certain extent, RISC technology simplifies the task of writing compilers for processors that utilize a RISC instruction set. Moreover, from a processor design standpoint, focus can be placed on implementing and optimizing those important and frequently-used instructions rather than having some complex but seldom-used instructions constrain the maximum operating efficiency. Because of the above-mentioned reasons and others, RISC processors are gaining popularity among workstation and even some lower-end computer manufacturers.
For RISC processors, it is common that very few instructions are actually memory access instructions. In fact, some implementations may have only two instructions, LOAD and STORE, that access memories. Typically, a few specialized "atomic" operations may also be supported by the RISC processor for synchronization and memory updates via concurrent processes. Even in such cases, LOAD and STORE instructions are by far the most frequently-used memory access instructions for RISC processors. The execution of a LOAD instruction will cause a processor register to be written with data associated with in a specified main memory address. Conversely, the execution of a STORE instruction will cause data resident in a processor register to be written to a memory hierarchy in association with a main memory address. The present disclosure provides an apparatus for adjusting control bits within a STORE instruction.